Printed circuit board having inductive vias

ABSTRACT

A printed circuit board includes at least one via providing a conductive path through the printed circuit board. The via comprises at least one axially extending conductive strip formed by cutting material from a metal barrel lining the interior wall of the via.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional PatentApplication, Serial No. 60/212,424, filed on Jun. 19, 2000, and U.S.Provisional Patent Application, Serial No. 60/218,112, filed on Jul. 13,2000.

BACKGROUND AND SUMMARY OF THE INVENTION

[0002] The present invention generally relates to printed circuitboards, and, more particularly, the present invention relates to printedcircuit boards having plated vias or holes.

[0003] In general, any structure that allows a signal to propagate fromone point to another is defined as a transmission line. As a signalpropagates along a transmission line, both a voltage and current arepresent. The ratio of these two parameters is defined as thecharacteristic impedance of the line. The characteristic impedance is aproperty that is determined solely by the material and geometry of thetransmission line. The characteristic impedance of the transmission lineis proportional to the ratio of the inductance and capacitance of theline. In general impedance is dependent upon frequency, but for linesthat are essentially lossless, such as connectors and high qualitycables, it can be considered constant.

[0004] When a transmission line is used to connect two points, ideallythe signal arriving at the receiver end will be the same as that whichentered the line at the driver end. However, if the transmission linechanges characteristic impedance at any point along the way, such asoccurs when a connector is placed between two circuit boards, thebehavior becomes more complicated. At the interface where such animpedance change occurs, partial reflections of the signal will becreated. These reflected waves will travel back toward the source wherethey may be re-reflected a second time. At each interface where animpedance change occurs, a reflected signal will be created. Thereflections caused by these impedance mismatches have the ability toalter the original signal transmission. They can be very problematicbecause they can cause logic circuits to switch inadvertently.Furthermore, as signal risetimes drop below 1 ns, connectors, chipsockets and even circuit board vias begin to create large enoughreflections as to potentially cause significant signal transmissionconcerns. Consequently, as clock rates increase and signal risetimesbecome short, all portions of the interconnection path need to be wellmatched to the impedances of the circuit boards and components theyinterconnect in order to avoid creating signal integrity problems.

[0005] Vias are created in printed circuit boards by forming metallicpads on the top and bottom surfaces of the board and on inner signallayers, drilling through holes through the pads and plating a hollowbarrel of metal between the pads. Vias allow connections to be madebetween the inner signal layers or planes and the outside surfaces ofthe board. Vias are also used to connect outside components (such asconnectors, surface mount components or integrated circuit chips) withthe internal signal layers in the board.

[0006] The impedance of a via can be determined from its inductance andcapacitance. The capacitance is created by the stray electric fieldpresent between the via and the various power or ground layers in thecircuit board. The inductance of the via is related to the magneticfield surrounding the portion of the via carrying the signal current.Typically the inductance of the via is quite small relative to itscapacitance. As such, most vias exhibit a very low impedance and are apoor match to typical circuit board trace impedances of 50-75 Ohms.

[0007] The impedance mismatches associated with vias are particularlydifficult to address. Whereas the geometry of connectors and chipsockets can, with care, be designed to match the impedance of thecomponents they will connect, few avenues are available to match theimpedance of vias to the elements they interconnect. Reducing the via'scapacitance or increasing the via's inductance will raise the via'simpedance and create an improved match. This improvement will improvethe capability to carry higher data rates from the circuit board throughthe via to the outside world. One may reduce the capacitance of the viasby reducing the length of the vias—for example, by counterboring thebackside of the boards. Counterboring does not allow routing of signalsto layers near the bottom of the printed circuit board. This limitationgreatly reduces signal routing possibilities.

[0008] Other similar techniques for reducing the capacitance of the viasinclude reducing the diameter of the vias or increasing the clearancebetween the vias and the internal circuit board layers. In each case theidea is to reduce the electrostatic coupling between the via barrel andthe conductor planes in the printed circuit board. Both of thesetechniques have drawbacks as well. Smaller diameter vias are moredifficult to plate, particularly in thick printed circuit boards.Increasing the clearance between the vias and the internal circuit boardlayers can render large portions of the layers useless in regions wheremultiple vias are placed close together such as where a connector mountsto the board.

[0009] According to one aspect of the present invention, a method forimproving the impedance match of a via having a conductive platinglining the inner wall thereof (also referred to herein as a “metalbarrel or cylinder”) includes a step of increasing the inductance of thevia and, thus, its impedance as well. According to another aspect of thepresent invention, the step of increasing the inductance of the viaincludes a step of inserting a small inductive coil in the via.According to still another aspect of the present invention, the step ofincreasing the inductance of the via having a metal barrel includes astep of tapping a screw thread into the metal barrel to transform itinto a short helical coil or strip. The inductance produced from thisapproach can be tightly controlled based on the pitch, width, and numberof turns of the screw thread implemented in the via. The geometry of thehelical coil can be tuned to obtain an inductance that allows theimpedance of the via to be matched to the impedance of the circuitboard.

[0010] According to a further aspect of the present invention, a methodof increasing the inductance of the via without altering its geometryincludes a step of plating the via with a paramagnetic or ferromagneticmaterial (such as nickel) to form a conductive barrel, instead ofplating the via with the usual tin-lead over copper compound.

[0011] According to still another aspect of the present invention, amethod for improving the impedance match of a via includes a step ofreducing the capacitance of the via and, thereby increasing itsimpedance. According to yet another aspect of the present invention, thestep of reducing the capacitance of the via having a metal barrelincludes a step of cutting material from the metal barrel to leave atleast one conductive strip or band extending axially along the wall ofthe via. According to still another aspect of the present invention, thestep of reducing the capacitance of the via having a metal barrelincludes a step of cutting material from the metal barrel to leave aplurality of conductive strips or bands extending axially along the wallof the via with axially extending, non-conductive spaces between theconductive strips.

[0012] Additional features of the present invention will become apparentto those skilled in the art upon a consideration of the followingdetailed description of the preferred embodiments exemplifiing the bestmode of carrying out the invention as presently perceived.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The detailed description particularly refers to the accompanyingfigures in which:

[0014]FIG. 1 is a perspective view of a dual layer printed circuit board(“PCB”) showing a conductive trace coupled to a conductive pad on thetop side of the PCB and a similar trace coupled to a conductive pad onthe bottom side of the PCB shown in phantom;

[0015]FIG. 2 is a perspective view similar to FIG. 1 showing the PCBbefore a hole is drilled therethrough to form a conductive viaconnecting the top and bottom conductive pads;

[0016]FIG. 3 is a perspective view similar to FIG. 2 showing the throughhole before it is plated;

[0017]FIG. 4 is a perspective view similar to FIG. 3 showing the throughhole after it is plated; and showing a conductive metal cylinder orbarrel (in phantom) ninig the internal wall of the through hole toprovide a conductive path between the opposed ends of the barrel andconnecting the conductive pads;

[0018]FIG. 5 is a perspective view similar to FIG. 4 showing the platedthrough hole after tapping a screw thread to transform it into a shorthelical coil or strip (in phantom) connecting the top and bottomconductive pads;

[0019]FIG. 6 is a perspective view similar to FIG. 5 showing the PCB inphantom, and showing the short helical coil connecting the top andbottom conductive pads in solid lines;

[0020]FIG. 7 is a perspective view of a PCB similar to FIG. 1 showing aconductive strip extending axially between the top and bottom conductivepads, and formed by broaching a plated through hole;

[0021]FIG. 8 is a top view of the FIG. 7 PCB showing the conductivestrip extending axially between the top and bottom conductive pads;

[0022]FIG. 9 is a top view similar to FIG. 8, but showing three radiallyspaced conductive strips extending axially between the top and bottomconductive pads, and separated by a plurality of non-conductive axiallyextending spaces;

[0023]FIG. 10 is a plan view of a multi-layer PCB comprising a pluralityof signal and ground planes, and having a via comprising a conductivemetal barrel lining a through opening therein;

[0024]FIG. 11 is a plan view of the PCB of FIG. 10 after two holes aredrilled on the opposite sides of the via such that each hole removesapproximately one quarter of the annulus comprising the via;

[0025]FIG. 12 is a sectional view of the PCB of FIGS. 10 and 11 througha ground plane, and showing a keep-out area surrounding the via and thetwo holes on the opposite sides thereof,

[0026]FIG. 13 is a sectional view of the PCB of FIGS. 10 and 11 throughan inner signal layer, and showing a signal trace connected to aconductive pad thereon;

[0027]FIG. 14 is a sectional view of a multi-layer PCB having aplurality of signal planes alternating with ground planes to form aground, signal, ground, signal and ground configuration, and showing apair of oppositely disposed conductive pads on top and bottom sides ofthe PCB, a conductive cylinder or barrel extending between theconductive pads and a coil connecting the two signal layers andschematically representing the inductance of the conductive via; and

[0028]FIG. 15 is an equivalent electric circuit schematicallyrepresenting the multi-layer PCB of FIG. 14.

DETAILED DESCRIPTION OF THE DRAWINGS

[0029] Referring to the FIGS. 1-6, a PCB 10 includes a conductive trace20 coupled to a conductive pad 22 on the top side 12 of the PCB 10, anda conductive trace 30 coupled to a conductive pad 32 on the bottom side14 of the PCB 10. The top and bottom conductive pads 22, 32 arevertically aligned. The conductive traces 20, 30 are coupled torespective circuits (not shown) on the top and bottom sides 12, 14 ofthe PCB. The PCB 10 may be either a dual layer PCB as shown in FIGS.1-6, or a multilayer PCB. The multilayer PCB comprises a number of PCBsthat are stacked on top of each other and joined together.

[0030] A through via or hole 40 is drilled through the top conductivepad 22, through the PCB 10 and through the bottom conductive pad 32 asshown in FIG. 3. The via 40 is then plated using any suitableconventional technique to provide a metal lining or barrel 42 inside thevia 40 as shown in FIG. 4. The metal barrel 42 is essentially a hollowmetal cylinder lining the internal walls of the hole 40 with an annularconductive pad 22, 32 about each end of the cylinder. The metal barrel42 provides a signal path between the conductive pads 22, 32 to routesignal from the top side 12 of the PCB 10 to the bottom side 14 of thePCB 10.

[0031] As previously indicated, vias exhibit stray capacitance in theelectrical path because of the plated barrel's proximity to otherconducting layers in the PCB, such as inner ground or power layers. Theproblem is particularly acute when vias are used for transmitting higherfrequency signals between the layers. In accordance with one aspect ofthis invention, the length of the conductive path through the via 40 isincreased by tapping a screw thread into the barrel 42 to transform itinto a short helical coil 44 extending axially between the opposed endsof the barrel 42. This approach also serves to reduce thecross-sectional area of the current path through the via 40. Theinductance produced from this approach can be tightly controlled basedon the pitch, width, and number of turns of the screw thread implementedin the via 40. Thus, this approach allows the impedance of the via 40 tobe closely matched to the impedance of the PCB 10.

[0032] Alternatively, as shown in FIGS. 7-9, one may reduce the straycapacitance exhibited by the metal barrel 42 by cutting (for example,broaching) the metal barrel 42 to remove vertical strips of metal fromthe barrel 42, leaving one or more conductive strips extending axiallyalong the wall of the via 40 with non-conductive spaces between theconductive strips. As previously mentioned, reduction of the straycapacitance will increase the impedance and reduce the impedancemismatch between the via 40 and the PCB 10, and thus improve the signaltransmission quality through the via 40. This improvement will improvethe capability to carry higher data rates from the PCB 10 through thevia 40 to the outside world. FIGS. 7 and 8 show one conductive strip 120extending axially between top and bottom conductive pads 122, 124.Alternately, a broach may have a triangular cross section (for example,a three cornered file) such that it cuts away three separate radiallyspaced, axially extending non-conductive spaces 136 leaving threeequi-spaced conductive strips 130 extending axially between top andbottom conductive pads 132, 134. It will be appreciated that severalbroach cross sections may be designed to remove different amounts orconfigurations of the barrel 42. This approach also reduces the crosssectional area of the current path through the via 40 to increase theinductance of the via 40 and, thus, its impedance as well.

[0033] FIGS. 10-13 illustrate another method for broaching material fromthe metal barrel of a via 152 to reduce the stray capacitance betweenthe via 152 and the ground planes 156 in a multi-layer PCB 150. FIG. 10shows a plan view of the PCB 150 having a via 152. The via 152 is in theform of a conductive metal barrel lining a through opening in the PCB150 as is typical practice. The PCB 150 may comprise alternating signaland ground layers or planes 154, 156 arranged in a stack-upconfiguration, for example, as shown in FIG. 14. The top, bottom andintermediate signal layers of the PCB 150 include conductive pads 158that are connected to the via 152. A generally oval-shaped keep-out area160 is provided in the ground planes 156 through which the via 152passes. The keep-out area 160 is shown by broken lines in FIGS. 10, 11and 13, and in solid lines in FIG. 12. The keep-out area 160 is sizedand shaped such that two additional through holes 162, 164 can bedrilled in the PCB 150 adjacent to the via 152 on opposite sides thereofwithout piercing through the ground planes 156 as shown in FIGS. 11-13.The center lines of the two holes 162, 164 lie on the same line as thecenter line of the via 152. The holes 162, 164 are about the same sizeas the conductive pads 158, and are spaced such that each hole 162, 164removes approximately one quarter of the ring comprising the via 152 onopposite sides thereof. FIG. 11 is a plan view of the PCB 150 after thetwo holes 162, 164 are drilled. FIG. 12 is a sectional view of the PCB150 through a ground plane 156, and showing a keep-out area 160 in solidlines. Typically, a ground plane 156 will not have a conductive pad 158.FIG. 13 is a sectional view of the PCB 150 through an inner signal layer154, and showing a signal trace 166 connected to a conductive pad 158 onthe inner signal layer 154. Alternatively, one may drill three holesaround the via 152 such as to leave only one axially extendingconductive strip in the via 152, instead of two axially extendingconductive strips on opposite sides of the via 152.

[0034] The two holes 162, 164 may be drilled after plating the throughhole in the PCB 150 to form the via 152. Alternatively, the plating ofthe via 152 may be done after the two holes 162, 164 are drilled on theopposite sides of the through hole in the PCB 150. If plating is doneafter drilling the two holes 162, 164 on the opposite sides of the via152, the via 152 must be first cleaned to remove debris from the PCB 150prior to plating, and care must be taken to avoid depositing metal onthe two side holes 162, 164.

[0035] Another aspect of the present invention is to plate less than afull barrel lining the wall of a hole or via. For example, a mask may beprovided to block plating from portions of the wall of the hole. Oneapproach may be to use a masking wax or coating covering the walls ofthe holes. This coating could then be selectively removed before platingsuch that only removed portions of the wall would be plated. Forexample, a tap may be used to remove a helical trace in the wall of thecoating so that a conductive helix is plated between the opposed ends ofthe hole. Alternatively, a broach may be used to remove radially spaced,axially extending strips of the coating so as to form axially extendingconductive strips between the opposed ends of the hole. Still anotherapproach for increasing the inductance of the via 40 without alteringits geometry requires the use of a different plating material instead ofthe usual tin-lead over copper material commonly utilized in theindustry. For example, plating the via with a paramagnetic orferromagnetic material (such as nickel) to form a conductive barrelbetween the pads.

[0036]FIG. 14 shows yet another approach for increasing the inductanceof a via 70. As shown therein, a multi-layer PCB 50 includes a groundlayer 52 (G1), a signal layer 54 (S1), a ground layer 56 (G2), a signallayer 58 (S2) and a ground layer 60 (G3). The layers 52-60 arealternately ground and signal, and are arranged in a stack-up, sandwichconfiguration. The PCB 50 includes a conductive pad 62 on the top side64 of the PCB 50, and a conductive pad 66 on the bottom side 68 of thePCB 50. The top and bottom conductive pads 62, 66 are verticallyaligned. A through via or hole 70 is drilled through the top conductivepad 62, through the PCB 50 and through the bottom conductive pad 66. Thevia 70 is then plated using any suitable conventional technique toprovide a metal lining or barrel 72 inside the via 70. The metal barrel72 is essentially a hollow metal cylinder lining the internal walls ofthe via 70 with an annular conductive pad 62, 66 about each end of thecylinder. The metal barrel 72 provides an electrical path between theinternal signal layers 54, 58 of the PCB 50, and between the conductivepads 62, 66 on the top and bottom sides 64, 68 of the PCB 50 to whichexternal components may be connected. The signal layer 54 includes aconductive trace 80 coupled to a conductive pad 82. Likewise, the signallayer 58 includes a conductive trace 84 coupled to a conductive pad 86.The conductive traces 80, 84 are coupled to circuit elements (not shown)in the signal layers 54, 58 respectively. A coil 90 schematicallyrepresents the inductance encountered as the current travels from thesignal layer 54 to the signal layer 58 of the PCB 50. Numeral 112schematically represents the stray capacitance between the metal barrel72 and the ground planes 52, 56 and 60.

[0037] As previously described, according to one aspect of the presentinvention, the step of increasing the inductance of the plated viaincludes a step of tapping a screw thread into the plated via totransform it into a short helical coil or strip. The inductance producedfrom this approach can be tightly controlled based on the pitch, width,and number of turns of the screw thread implemented in the via. Thegeometry of the helical coil can be tuned to obtain an inductance thatallows the impedance of the via to be matched to the impedance of thecircuit board.

[0038] According to yet another aspect of the present invention, thestep of increasing the inductance or reducing the capacitance of theplated via includes a step of cutting material from the plated via (forexample, by broaching) to leave at least one conductive strip or bandextending axially along the wall of the via. According to still anotheraspect of the present invention, the step of increasing the inductanceor reducing the capacitance of the plated via includes a step of cuttingmaterial from the plated via (for example, by broaching) to leave aplurality of conductive strips or bands extending axially along the wallof the via with axially extending non-conductive spaces between theconductive strips. According to a further aspect of the presentinvention, the step of increasing the inductance of the via includes astep of plating the via with a paramagnetic or ferromagnetic material(such as nickel) to form a conductive barrel between the pads, insteadof plating the via with the usual tin-lead over copper compound.

[0039]FIG. 15 shows an equivalent circuit of the PCB 50 shown in FIG.14. The electrical components of the PCB form a transmission line 100between a first set of terminals 102, 104 and a second set of terminals106, 108. The inductive coil 90 representing the inductance of the via70 is coupled in series between the terminals 102, 106 of thetransmission line 100. Equivalent capacitance 110 of the via 70represents the summation of all stray capacitances 112 shown in FIG. 14.One half of the equivalent capacitance 110 is represented as coupledacross the first set of terminals 102, 104 of the transmission line 100.The other half of the equivalent capacitance 110 is shown as coupledacross the second set of terminals 106, 108 of the transmission line100. The best impedance match occurs when the characteristic impedanceof the transmission line 100 is equal to the square root of a fractionequal to the inductance of the coil 90 in the numerator and thecapacitance of the equivalent capacitance 110 in the denominator. Inother words, the best impedance match occurs when the inductance of thecoil 90 is equal to the square of the characteristic impedance of thetransmission line 100 multiplied by the capacitance of the equivalentcapacitance 110.

[0040] Although the present invention has been described in detail withreference to certain preferred embodiments, variations and modificationsexist within the scope and spirit of the present invention as describedabove.

1. A method for increasing the impedance of a via providing a conductivepath through a printed circuit board, the via comprising a conductivemetal barrel lining an opening through the printed circuit board, themethod including a step of cutting material from the metal barrel toleave at least one conductive strip extending axially along the wall ofthe opening.
 2. The method of claim 1, wherein the at least one axiallyextending conductive strip extends between the ends of the barrel. 3.The method of claim 1, further including a step of providing aconductive pad adjacent to one end of the barrel prior to the step ofcutting material from the metal barrel to leave at least one axiallyextending conductive strip.
 4. The method of claim 1, further includinga step of providing a conductive pad adjacent to each end of the barrelprior to the step of cutting material from the metal barrel to leave atleast one axially extending conductive strip.
 5. The method of claim 1,wherein the step of cutting material from the metal barrel comprisesusing a broach to form the at least one axially extending conductivestrip.
 6. The method of claim 1, wherein the step of cutting materialfrom the metal barrel comprises drilling at least one hole adjacent tothe barrel to leave at least one axially extending conductive strip. 7.The method of claim 1, wherein the step of cutting material from themetal barrel comprises drilling two holes on the opposite sides of thebarrel to leave two conductive strips extending axially along the wallof the opening on opposite sides thereof.
 8. The method of claim 7,wherein the two conductive strips extending axially along the wall ofthe opening are separated by two axially extending air spaces.
 9. Themethod of claim 7, further including a step of providing a conductivepad adjacent to one end of the barrel prior to the step of drilling twoholes on the opposite sides of the metal barrel to leave two axiallyextending conductive strips.
 10. The method of claim 1, wherein the stepof cutting material from the metal barrel comprises drilling a pluralityof holes around the barrel to leave a plurality of strips extendingaxially along the wall of the opening separated by a plurality ofaxially extending air spaces.
 11. A method for increasing the impedanceof a via providing a conductive path through a printed circuit board,the via comprising a conductive metal barrel lining an opening throughthe printed circuit board, the method including a step of cuttingmaterial from the metal barrel to leave a plurality of radially spaced,axially extending conductive strips separated by a plurality of axiallyextending non-conductive spaces.
 12. The method of claim 11, wherein theplurality of radially spaced, axially extending conductive strips extendbetween the ends of the barrel.
 13. The method of claim 11, wherein thestep of cutting material from the metal barrel comprises using a broachto cut the plurality of radially spaced, axially extending conductivestrips.
 14. A printed circuit board including at least one via providinga conductive path through the printed circuit board, the via comprisingat least one axially extending conductive strip formed by cuttingmaterial from a metal barrel lining the interior wall of the via. 15.The printed circuit board of claim 14, wherein the at least one axiallyextending conductive strip extends between the ends of the via.
 16. Theprinted circuit board of claim 14, wherein the at least one axiallyextending conductive strip is coupled to a conductive pad adjacent toone end of the barrel.
 17. The printed circuit board of claim 14,wherein a broach is used to cut the at least one axially extendingconductive strip.
 18. A printed circuit board including at least one viaproviding a conductive path through the printed circuit board, the viacomprising a plurality of radially spaced, axially extending conductivestrips separated by a plurality of axially extending, non-conductivespaces, the axially extending conductive strips being formed by cuttingmaterial from a metal barrel lining the interior wall of the opening inthe printed circuit board.
 19. The printed circuit board of claim 18,wherein the plurality of radially spaced, axially extending conductivestrips extend between the ends of the via.
 20. The printed circuit boardof claim 18, wherein a broach is used to cut the plurality of radiallyspaced, axially extending conductive strips.
 21. A method for increasingthe impedance of a via providing a conductive path through a printedcircuit board, the method including the steps of providing an openingthrough the printed circuit board, covering the wall of the opening witha masking material, selectively removing portions of the maskingmaterial from the wall of the opening, and plating removed portions ofthe wall with a conductive material.
 22. The method of claim 21, whereina tap is used to cut a helical trace in the masking material so that aconductive helical strip is formed along the wall of the opening betweenthe opposed ends thereof.
 23. The method of claim 21, wherein a broachis used to cut at least one axially extending strip in the maskingmaterial so that at least one axially extending conductive strip isformed along the wall of the opening between the opposed ends thereof.24. The method of claim 21, wherein a broach is used to remove aplurality of radially spaced, axially extending strips in the maskingmaterial so that a plurality of radially spaced, axially extendingconductive strips are formed along the wall of the opening between theopposed ends thereof.
 25. The method of claim 21, wherein the maskingmaterial is wax.
 26. The method of claim 21, further including the stepof removing the remaining portions of the masking material after thestep of plating removed portions of the wall with a conductive material.